The present invention relates to a display drive method and a display apparatus which drive display element, and more particularly to a display drive method and a display apparatus which are adapted for outputting, on the basis of concept of subfield, corresponding data every the subfield by PWM (Pulse Width Modulation).
This Application claims priority of Japanese Patent Application No. 2001-357784, filed on Nov. 22, 2001, the entirety of which is incorporated by reference herein.
Various display elements utilizing light modulation element are widely known as display element. Further, e.g., in displays using such light modulation element as display element, PWM (Pulse Width Modulation) system is known as display drive system for light modulation. In this PWM system, time width of condition where, e.g., light source luminance is caused to be constant to thereby conduct gradation representation.
In the PWM system, particularly the drive system utilizing subfield is known. Here, the subfield is also called bit plane. This drive system is based on the above-described binary display state by ON/OFF (emitting (white)/non-emitting (black)), and is adapted to form combination of bit planes in which time width is set by weight of data bits. Display elements are driven by combination of these plural bit planes (subfields) to thereby represent gradation.
In performing display drive by the PWM system as described above, it is necessary to conduct weighting by time width. Further, time width of the least significant bit in this case can be expressed by the following formula.
                              T          LSB                =                              t            f                                              2              n                        -            1                                              (        1        )            
TLSB: Least Significant Bit Time Width
tf: frame frequency
n: number of bits
Assuming that time width is based on the above-mentioned formula (1), if the frame frequency is equal to 120 Hz on the premise that gradation representation is performed by, e.g., 10 bits, time width of the least significant bit (least significant bit time width) of plural subfields becomes equal to 8 μs.
Time change of rewrite operation of subfield data is shown as drive operation in the general subfield system is shown in FIG. 46. In this case, the case where rewrite operation of one field is conducted by three subfields of subfields 0, 1, 2 is shown as the case where gradation is represented by 3 bits. In this figure, field n and the next field n+1 are shown, wherein the longitudinal direction indicates vertical scanning direction (ROW direction) and the lateral direction indicates time passage.
In the case where the display element is liquid crystal, a.c. drive is conducted in order to avoid deterioration of liquid crystal by d. c. drive in a manner well known. However, here, polarity of subfield data is inverted every field time period to thereby perform a.c. drive. In this case, as subfield data, positive data is outputted in the field n and negative data is outputted in the field n+1.
In FIG. 46, at the time period of the preceding field n, subfield data 0 which is positive in polarity corresponding to subfield 0 is first outputted and is written in line-sequential manner in accordance with time width by a predetermined weighting. When picture as subfield 0 is assumed to be formed as the result of the fact that write operation of the subfield data 0 has been conducted with respect to all pictures, subfield data 1 which is positive in polarity corresponding to the subfield 1 is subsequently similarly written in line-sequential manner by time half width by a predetermined weighting. Thus, picture as subfield 0 is formed. Further, subfield data 2 which is positive in polarity corresponding to subfield 2 is subsequently written in line-sequential manner to form picture as the subfield 2.
As the result of the fact that pictures as subfields 0, 1, 2 are formed in sequence in a manner as described above at one field time period, rewrite operation of data with respect to field n is first completed.
Subsequently, rewrite operation of data with respect to field n+1 is conducted. In this instance, in view of necessity of inverting drive for the purpose of preventing degradation of liquid crystal, subfield data is inverted to allow it to be negative in polarity. Thereafter, subfield data are written in a manner as described above to thereby sequentially form pictures as subfields 0, 1, 2.
Meanwhile, as understood from the explanation with reference to FIG. 46, rewrite operations of subfield data at respective subfield time periods are conducted in line-sequential manner. Accordingly, it is required that rewrite operation (output) of one subfield data is executed within the time of the least significant bit time width. Data transfer speed (rate) for transferring data to display device comprising display elements will be also determined in correspondence thereto.
As a practical example, the case where the frame frequency is equal to 120 Hz at gradation representation by 10 bits will be considered. In this case, as previously described, the least significant bit time width becomes equal to 8 μs by the formula (1). Further, under this condition, the display device comprising display elements is assumed to be in conformity with the standard of WXGA (Wide eXtended Graphics Array) having the number of pixels of 1280×768. In order to cope with such configuration, even if, e.g., data bus width is caused to be 32 bits, data transfer speed (rate) becomes equal to 3.8 GHz. For example, when data transfer speed (rate) is raised to such degree, realization of the display device would not become actual in the case where ability, etc. of the existing circuit, etc. is taken into consideration. Accordingly, also in the display drive based on the concept of subfield, it is required that the data transfer speed (rate) can be caused to be as low as possible.
Also in the display drive based on the concept of subfield as explained from now on, in the case where display element is liquid crystal, it is necessary to employ a.c. drive. Further, in the case of display drive by the general subfield system shown in FIG. 46, common potential to be applied to the common electrode formed in solid plane form on the entirety of display screen in a manner opposite to pixel electrodes of liquid crystal display elements is caused to be constant. Under such condition, positive/negative data are applied to pixel electrodes with this common potential being as reference to thereby realize a.c. drive.
In the case of such a.c. drive, when absolute value of liquid crystal drive maximum voltage level of each polarity is assumed to be Vmax, pixel switches which form respective pixels are required to have withstand voltage corresponding to voltage width of ±Vmax. For example, increase in withstand voltage of the pixel switch leads to enlargement of size of the pixel switch. Accordingly, the number of pixels per unit area becomes small. Thus, this results in obstacle to, e.g., hastening of high fineness and/or miniaturization of the liquid crystal display device.